1. Field of the Invention
The present invention relates to a method for driving a solid-state imaging device using a CCD (Charge Coupled Device) or the like.
2. Description of the Prior Art
Solid-state imaging devices using CCDs are widely used for an apparatus such as a video camera and digital still camera.
One problem to be solved in solid-state imaging devices using, for example, CCDs is a blooming phenomenon. The blooming phenomenon is a phenomenon that when more light than the saturation light amount of a photodiode (PD) portion of in a solid-state imaging device is incident thereon, signal charge overflows the photodiode portion to cause surplus charge to flow into surrounding pixels, with a result that a bright region exposed to light extends even to a portion not exposed to light in a taken image. The blooming phenomenon may occur at any position even other than a region for receiving light, for example in a vertical transfer unit, as long as it is provided with a p-n junction and may serve as a photodiode.
To suppress the blooming phenomenon, an overflow drain has been conventionally formed in CCDs to draw out surplus charge to a substrate side, for example. Specifically, an n-type substrate is provided on its surface with a p well region which is provided on its surface with an n.sup.+ region such that the p well region and the n.sup.+ region constitute a photodiode. A reverse bias voltage is applied between the p well region and the n substrate to completely deplete the p well region. When intense light is incident on a photodiode portion in the vertical overflow drain structure, a potential at the photodiode is reduced to cause a reduction in a potential at an n.sup.+ -p junction, thereby discarding surplus charge to the n-type substrate side.
When the vertical overflow drain structure is employed, the blooming phenomenon can be suppressed. Simultaneously, the application of a sweep pulse to the photodiode portion can draw out accumulated signal charge in the substrate direction to enable electronic shuttering to be performed. For electronic shuttering, a low operating voltage is desirable for sweeping away charge to the substrate side.
However, in the aforementioned vertical overflow drain structure, since variations in an impurity concentration in the n-type substrate cause variations in the saturation capacity or a read-out potential among respective photodiodes, fixed pattern noise referred to as swirl may occur on a taken image.
To suppress the generation of the swirl as well as the blooming phenomenon, Japanese Patent Publication No. 4-24872 (JP, 04024872, B2) discloses a solid-state imaging device in which, in a pixel region including a photodiode of a CCD, an n-type substrate is provided thereon with an n.sup.+ -type epitaxial layer having an n-type impurity diffused therein at a relatively high concentration and an n-type epitaxial layer having an n-type impurity diffused therein at a relatively low concentration in this order, and the n-type epitaxial layer is provided therein with a p region (so-called p well region) which is provided on its surface with an n-type layer such that the p region and the n-type layer constitute a photodiode. The solid-state imaging device makes it possible to locate a depletion layer edge in the n.sup.+ -type epitaxial layer whenever a reverse bias voltage is applied between the n-type substrate and the p region with settings of layer thicknesses and impurity concentrations. In order to locate the depletion layer edge in the n.sup.+ -type epitaxial layer whenever a reverse bias voltage is applied between the n-type substrate and the p region, it is required to determine the thickness and impurity concentration of the n-type layer such that the depletion layer edge is located within the n-type layer in a state where a reverse bias voltage is at 0 V. According to a technology disclosed in JP, 04024872, B2, it is possible to reduce a reverse bias voltage to be applied to the solid-state imaging device and to prevent the generation of swirl by locating the depletion layer edge in the n.sup.+ -type epitaxial layer having a uniform distribution of the impurity concentration.
FIG. 1 is a schematic sectional view showing a configuration of a pixel portion of the solid-state imaging device disclosed in JP, 04024872, B2. FIG. 2 is a diagram showing potential distribution in a depth direction in a photodiode portion of the solid-state imaging device shown in FIG. 1.
On an n-type substrate 11 made of silicon, an n.sup.+ -type epitaxial layer 12 is formed as a first epitaxial layer with a thickness of 15 .mu.m and an n-type impurity concentration of 1.times.10.sup.15 cm.sup.-3 on which an n-type epitaxial layer 13 is formed with a thickness of 2 .mu.m and an n-type impurity concentration of 1.times.10.sup.14 cm.sup.-3. The n-type epitaxial layer 13 is provided on its surface with a p region 14 (so-called p well layer) having a p-type impurity diffused therein which is further provided on its surface with an n layer 17 having an n-type impurity diffused therein. The p region 14 and n layer 17 form a p-n junction which serves as a photodiode portion. In the photodiode portion, the p region 14 has a thickness of 1.2 .mu.m and a p-type impurity concentration of 5.times.10.sup.15 cm.sup.-3, while the n layer 17 has a thickness of 0.8 .mu.m and an n-type impurity concentration of 5.times.10.sup.16 cm.sup.-3. A p-n junction between the n-type epitaxial layer 13 and the p region 14 is an abrupt junction in which a width of a depletion layer extending from the junction interface to the n-type epitaxial layer 13 side can be simply calculated based on respective impurity concentrations of the n-type epitaxial layer 13 and p region 14. When a calculation is made using the example herein shown, it can be seen that a depletion layer edge is located within the n.sup.+ -type epitaxial layer 12 beyond the n-type epitaxial layer 13 even on condition that a reverse bias voltage is at 0 V since the n-type epitaxial layer 13 has a low impurity concentration and a thin film thickness.
Additionally, a transfer gate comprising an p layer 15 extending more deeply than the p-n junction of the photodiode, an n layer 16 formed on a surface of the p layer 15, and a transfer electrode 19 acting as a gate electrode for the p layer 15 is provided for transferring accumulated charge in the photodiode portion generated with incident light to a charge transfer unit (not shown) of the CCD. In the example herein shown, the charge accumulated in the photodiode portion is transferred to the right in FIG. 1, and a p.sup.+ layer 18 is provided for preventing the charge from being transferred to the left in FIG. 1. The n-type epitaxial layer 13, p region 14, p layer 15, n layers 16, 17 and p.sup.+ layer 18 are formed in an n-type epitaxial region serving as a second epitaxial layer, and the second epitaxial layer is formed on the n.sup.+ -type epitaxial layer which serves as the first epitaxial layer. Additionally, light shield film 20 is formed such that light is incident only on the photodiode portion.
In the conventional solid-state imaging device shown in FIG. 1, a reverse bias voltage (blooming suppressing voltage) is applied between the p region (p well region) 14 and the n-type substrate 11 such that the depletion layer edge is located within the n.sup.+ -type epitaxial layer 12. FIG. 2 conceptually shows potential distribution in the photodiode portion in a depth direction when the blooming suppressing voltage is applied in the aforementioned manner. A hatched portion in FIG. 2 represents a region which is not depleted. When light is incident on the photodiode portion, negative charge is accumulated corresponding to the peak portion of the potential above the point at which "barrier" is written on the potential curve in FIG. 2. However, when intense light is incident, the p-n junction of the photodiode portion becomes shallow to cause surplus charge to be drawn out to the substrate side beyond the barrier.
FIG. 3 is a graph conceptually showing a relationship between a substrate potential relative to the p region 14 and saturation charge amount Q.sub.max of the photodiode portion when the depletion layer edge is located within the n.sup.+ -type epitaxial layer 12 whenever a reverse bias voltage is applied between the n-type substrate 11 and the p region 14. It can seen that when a blooming suppressing voltage is applied to increase saturation charge amount Q.sub.max, the saturation charge amount greatly varies with a slight change in the substrate potential to make it difficult to control the blooming suppressing voltage. If a certain variation is expected in the saturation charge amount of the photodiode portion, it is required to set imaging conditions or the like of the solid-state imaging device based on a smaller one of expected saturation charge amounts, thus causing a reduced dynamic range, a deteriorated signal to noise ratio, or the like.